Community Newsletter: November 2017
IN THIS ISSUE:
- Message from the Chair
Lu Dai recaps his first year as Chair
- DVCon around the Globe
The latest from the Design & Verification Conference and Exhibition worldwide
- SystemC Evolution Day Wrap-up
A successful day of discussions centering around SystemC
- Q & A with SystemRDL Working Group Chair
See what Miles McCoo has to say about the standard
- An Update on SystemC CCI from the Working Group Chair
Trevor Wieman discusses the latest developments with the draft Configuration standard
- Portable Stimulus News
Gabe Moretti interviews working group leaders
- Technical Spotlight
SystemRDL in public review
- New UVM Video Tutorial Available
Introducing IEEE 1800.2 - The Next Step for UVM
In my first year as Chair of Accellera I have been able to see first-hand the hard work and dedication of the members of Accellera. We have accomplished a great deal in 2017:
- IEEE 1800.2 for UVM was approved as an IEEE standard and is available at no charge under the Accellera-sponsored IEEE Get Program.
- The emerging Portable Stimulus standard just closed its public review period and is on track to release version 1.0 in the first half of 2018.
- The inaugural DVCon China and DVCon Japan conferences were well received with plans well underway for 2018; DVCon U.S., DVCon India, and DVCon Europe all enjoyed continuing success, helping the DVCon conference and exhibition to reach more regions across the globe than ever before.
- SystemRDL 2.0 is currently in public review. If you are interested in this standard, please download the draft and provide feedback.
To continue to evolve our standards, especially user-driven compatibility standards such as Multi-Language and UCIS, we encourage you to contact us and, when available, participate in our online forums and community pages. The forums provide an opportunity to discuss experiences with the standards, make requests for updates, and provide feedback to the working groups. Accellera is user-focused and user-driven. Without your participation and sharing of ideas, our standards couldn't evolve.
Because input from the broad design and verification community is important to our growth, we have expanded our membership to include small start-up companies and universities at a lower cost. Their input will be invaluable as we work together to collaborate to innovate and deliver global standards. The next membership year begins on January 1st. See our membership page for more information and to download the Membership Agreement.
As we look toward 2018, we would also like your feedback on our conferences, their technical tracks and tutorials, and what you would like to see more of as we plan each of their programs to ensure that they continue to add value to you and the community.
I would like to thank all of our working group members and all of those that have contributed to the evolution of our standards over this past year. I look forward to our continued success in 2018.
I hope you all have a wonderful holiday season.
Lu Dai, Accellera Systems Initiative Chair
DVCon India was held in Bangalore in September. Approximately 500 attendees and exhibitors participated in the two-day conference and exhibition. The conference opened with a traditional lamp-lighting ceremony and welcome remarks by Prasanna Kesavan Venkatesan, General Chair of DVCon India 2017. Highlights included insightful keynotes delivered to a packed room of more than 400 attendees by Dr. Christopher Tice, vice president, Verification Continuum Solutions, Synopsys and Vishal Dhupar, MD, NVIDIA. Their speeches outlined the industry’s next challenges: "The Software Gap" and "The Re-Emergence of Artificial Intelligence Based on Deep Learning Algorithms."
DVCon Europe was held last month in Munich. In its fourth year, there were approximately 300 attendees and 21 exhibitors participating from 22 countries. Highlights included two keynotes: "Consumer MEMS Products: Quality Rather than Commodity," presented by Dr. Horst Symanzik of Bosch Sensortech and "Driving Virtual Prototyping of Automotive Electronics," presented by Berthold Hellenthal from the Audi Competence center for Electronics and Semiconductors. In addition to the 16 informative tutorials, nine papers and two panel sessions, there was also a special session on 5G that provided some valuable insight into the next generation of cellular communication. DVCon Europe 2018 will be held October 24-25, 2018 at the Holiday Inn Munich City Centre.
DVCon U.S. 2018 will be held February 26 - March 1, 2018 at the DoubleTree in San Jose, California. On December 5th early registration will open and the program will be available online. DVCon U.S. has added new short workshops to the program this year to give smaller companies more options to participate. Over the course of the four-day program, attendees will be able to choose from numerous papers, tutorial, and posters as well as two panels and an expo. The conference will begin on Monday with Accellera Day, which will have a morning tutorial focused entirely on the emerging Portable Stimulus standard, as well as afternoon tutorials, including one on UMV that will introduce engineers to the new reference implementation aligned with IEEE 1800.2.
DVCon China 2018 will be held April 18, 2018 at the DoubleTree by Hilton in Shanghai-Pudong. In its second year, the conference has a highly technical focus on System and IC design, verification, and integration. It is a very practical and industry-focused conference on EDA standards and the process of standardization. The deadline for abstracts has been extended to November 27th. For more information or to submit an abstract, visit here.
As a follow-up to the first SystemC Evolution Day in May 2016, the SystemC user community met again right after DVCon Europe 2017 for the second edition of this full day technical workshop to discuss the evolution of the various SystemC standards. With more than 60 participants, the Accellera-sponsored event was sold out again, with representatives from over 25 companies and academic institutions in attendance.
The main objective of the SystemC Evolution Day series is to identify areas in which to align and accelerate the different SystemC standardization initiatives within Accellera and work towards solution proposals for standards inclusion. The discussions were centered around four in-depth technical sessions in the fields of SystemC checkpointing support, register inspection and debug, datatypes, and protocol modeling for high-level synthesis. During the open wrap-up session, additional topics were discussed such as clock/reset/interrupt modeling, parallel/distributed simulations, and others. The material and presentations are shared with the Accellera SystemC Working Groups for follow-up discussions.
With the continuing success of this workshop format and the very positive feedback from the attendees, the organization committee is exploring options to further enhance the format for future editions of the SystemC Evolution Day.
Q: What are the key issues your working group is currently addressing?
A: SystemRDL 2.0 adds a number of productivity and correctness features. For productivity, we are moving beyond simple key/value pairs and have added structs and enums. Design reuse is enhanced through parameterized components and the ability to turn off subcomponents (isPresent) enables a single SystemRDL file to represent multiple configurations (i.e., SKUs/bins/fused).
Regarding correctness, SystemRDL lives in an ecosystem with other standards. We've added a mapping between UVM/IP-XACT <-> SystemRDL access modes. RTL paths will enable validation tools to verify registers by going straight to the source. We've also added test constraints to give additional hints to validation tools.
Q: What do you hope to learn from the public review?
A: The SystemRDL Working Group has been largely the same group of people for the last couple of years. We need additional eyes outside of our core group to review it to ensure we're not making any shared assumptions and are not taking anything for granted. We want to make sure the specification is as clear as possible so its usefulness is apparent.
Q: How is SystemRDL different from IP-XACT registers?
A: IP-XACT is friendly to computer programs, but difficult for humans. SystemRDL is more like SystemVerilog or other languages whose features focus on making it possible for people to translate design decisions into something EDA tools can understand. SystemRDL can be edited in your favorite text editor. IP-XACT registers can be edited by hand, but no one would want to.
Q: What else would you like readers to know about SystemRDL?
A: We hope to raise more awareness in the design community of the existence and usefulness of this standard. I think that SystemRDL 2.0 is a large step forward. SystemRDL 1.0 covered the basics, but for complex designs, so much more was needed. Designers need to specify implementation details and validation hints. BIOS often needs more. This information can be include in auto-generated documentation along with the basic structure (addressing, field layout, access modes). Common structures need to be given in uniform ways (i.e., PCI and memory map attributes). The list goes on. All of these tasks become a bit easier with SystemRDL 2.0. I believe most companies creating SoCs or IP would benefit from this standard as it simplifies a portion of design and documentation that nearly every system requires.
The SystemC Configuration, Control and Inspection (CCI) WG is finalizing a draft Configuration standard for public review. The charter of this WG is to provide standards allowing tools to seamlessly and consistently interact with models to provide essential capabilities. The WG's roadmap includes features such as register introspection and saving and restoring model state. The first order of business has been to define a standard for runtime configuration.
The ability to configure SystemC models makes them more nimble, flexible and reusable. Some examples of model configuration are cache size, the filename of a software image to be preloaded, and whether execution tracing is enabled for a specific model. Commercial SystemC simulation tools provide model configuration libraries that enable tool features such as discovering where model configurability exists, preloading initial settings from a configuration file, monitoring configuration settings, and updating configuration settings on-the-fly. Because these model configuration libraries are proprietary, the tools don't work very seamlessly or effectively when models are developed using a model configuration library that is not its own. The number of model configuration libraries in use today is even greater than the number of SystemC simulation tools, compounding this problem. The SystemC Configuration standard is important because it will allow significant, if not full, utilization of any compliant tool's configuration capabilities with any model developed using a compliant model configuration library.
The CCI WG has addressed several key concerns in defining this standard. Of critical importance is the ability to interact with tools for which a portable value representation has been provided, along with information about configuration parameters (configurable entities instantiated within models) including a description and flexible metadata. The standard also has to be sufficiently capable to replace existing solutions. Among the fundamental features are avoiding name clashes with elements of the SystemC object hierarchy, looking up and accessing configuration parameters, restricting access to parameters, preloading configuration settings, callbacks for parameter creation/destruction as well as value access, traceability of parameter value updates, and support for user-defined parameter value types. Additionally, the standard has been architected to allow existing model configuration solutions to achieve compliance through a bridge, avoiding the necessity to update models and streamlining migration.
Preliminary and high-level feedback has been obtained during draft standard preview tutorials at DVCon Europe 2016, DVCon U.S. 2017, and DVCon India 2017. The 90-day public review will provide an opportunity for the SystemC community to take the standard for a "test drive" and provide much more specific and detailed feedback. The public review package is comprehensive including the LRM, a proof-of-concept implementation, 20+ examples with walkthroughs, and an overview tutorial. The CCI WG is interested in all feedback but especially on completeness of the feature set, ability to bridge legacy solutions, and ease of understanding and use. Watch for the public review announcement soon. We look forward to hearing from you.
Gabe Moretti, editor and Accellera co-founder, interviewed leaders of the Portable Stimulus Working Group at the Design Automation Conference this year to discuss the development of the emerging standard. Read the full interview >
The tutorial "Introducing IEEE 1800.2 - The Next Step for UVM" discusses the changes that UVM underwent during the IEEE standardization process to become IEEE 1800.2. The tutorial examines the impact these changes will have on your existing verification environments including how to debug and regold those environments, thus improving your ability to share verification IP among globalized teams. The tutorial concludes with an application of UVM RTL for designers.
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