Community Newsletter: August 2016
IN THIS ISSUE:
- Message from the Chair
It’s a busy summer at Accellera!
- DVCon Europe
Welcome to DVCon Europe from General Chair Oliver Bell
- DVCon India
Welcome to DVCon India from General Chair Gaurav Jalan
- DVCon U.S.
Deadlines for 2017 participation are fast approaching! All 2016 Accellera Day tutorials are now available for download
- DVCon China
Coming to Shanghai April 19, 2017!
- Working Group Member Highlight
Martin Barnasconi commended for his significant contributions to Accellera
- SystemC Japan
Engineers in Japan attend a full day of SystemC education
- Accellera in the News
SystemC supplemental material relicensed under Apache 2.0
- Portable Stimulus Tutorial Webinar
Planning is well underway for a three-part series
- SystemC Evolution Day
Presentations now available for download
It's shaping up to be a busy summer at Accellera. With the need for design and verification engineers around the globe to have access to the latest information regarding standards and technology development, we are excited to add DVCon China to our family of DVCon conferences on April 19, 2017 in Shanghai. Our team is working diligently with the local interested groups to ensure that China, like our other DVCon conferences, is targeted at meeting the regional needs of the attendees. The addition of China brings the reach of our DVCons to four countries on three continents. In its third year, DVCon India is just around the corner in September, and DVCon Europe will be held in October. DVCon U.S. will hold its 29th conference at the end of February 2017.
We have also recently achieved a significant milestone at Accellera: we have just completed the relicensing of all SystemC supplemental material under the Apache License, version 2.0. We have been working with all of the contributing companies over the last 18 months to make sure SystemC users have a clear path to contribute improvements to the supplemental material under the industry-preferred Apache 2.0 license. We are thankful to all who helped make this happen.
We look forward to seeing you at our upcoming DVCons, and we hope you have a wonderful summer!
Shishpal Rawat, Accellera Systems Initiative Chair
Summer, a time of vacations with family and friends, is for many the best season of the year. There are only few weeks before Munich's fifth season will start, the famous Oktoberfest. Right after Munich will host the third DVCon Europe on October 19-20, 2016.
It's fantastic how quickly DVCon Europe has been established as the place to be for the European design and verification community. It's not surprising, given its comprehensive, practical and broad program that attracts engineers looking for an update on leading-edge electronic development techniques. There are so many excellent reasons for a visit to DVCon Europe.
This year's program is better than ever! Each day will start with a keynote held by prominent Industry speakers. Hobson Bullman from ARM will kick off DVCon with an overview about the current methodology and infrastructure challenges being faced by ARM, and he will discuss solutions for IP delivery to a demanding partner base across a wide variety of markets. The focus of the first day is Tutorials. Besides Virtual Prototyping and UVM, there will be an increased prominence on Formal Verification techniques.
On day two Juergen Weyer from NXP will present "The Road Ahead for the Securely Connected, Self-Driving Car." Juergen will highlight ongoing developments and next-generation solutions to enable securely connected and self-driving cars. Mixed in with a broad range of papers, Functional Safety is a related mega-verification challenge that will be debated by distinguished experts in a special panel.
DVCon Europe provides a great learning experience and is well-suited for all who want to get an intense, but practical, overview on the latest design and verification challenges and solutions, as well as those who wish to go deep on a specific topic. Primary areas of the program include System Level, Virtual Prototyping, Advanced Verification with UVM and Formal, Design for Functional Safety, IP Reuse, Mixed-Signal and Low Power Techniques. The papers, presentations and panels are focused on the practical application of the latest innovative design and verification techniques for connected systems of systems, such as smart phones, wearables and cars, transforming into mobile datacenters with onboard sensors and computing.
The DVCon Europe Steering Committee works hard year-round to provide an attractive program for you, based on your comments and requests. At last year's DVCon Europe a well-attended 90-minute Birds-of-Feather session on SystemC attracted significant attendee interest, and this has inspired a full day special interest track focused on SystemC standardization and evolution. In addition, the Accellera SystemC Evolution Day, held earlier this year at Campeon Munich, was a clear "spinoff" from DVCon Europe demonstrating a very active European community in this area.
The "local Euro" networking opportunities are another important reason to attend the event. We are all aware of the importance of our own networks, which stay with us even as our careers evolve. The Gala Diner on the eve of the first day, included as part of the conference fee, is a perfect opportunity to extend your network. Additionally, the sponsored lunches, coffee breaks and receptions all represent opportunities to catch up with your colleagues and friends all over the continent.
DVCon Europe includes an attractive exhibition, which continues to grow. It's great to see that, in addition to the established "Big 3" EDA companies, a thriving number of smaller EDA players are looking to present themselves to electronics engineers and managers from all over Europe and beyond. All DVCon Europe sponsors, large and small, help to make this key event in downtown Munich a reality.
Summer is a time of open-air festivals in Munich, including a recent classical concert in Munich's Odeonsplatz. It was fascinating for me to see the virtuous collaboration of the conductor and his orchestra mastering the complexity of Beethoven Symphony No9. I am reminded that European engineers master similar complex verification challenges leveraging various technologies, difficult processes, and perfectly executed interactions. DVCon Europe reveals essential methodologies and flows for mastering the complex verification of connected systems in the age of the "Internet of Things."
Last but not least, keeping DVCon Europe local makes it easier to attend despite tight travel budgets. Munich is a lovely city, worth a visit even for just a few hours. The famous "Weltstadt mit Herz" is closely located to the Bavarian Alps. So, come and enjoy DVCon Europe, as well as all the other things this beautiful city has to offer.
See you in Munich at DVCon Europe!
Oliver Bell, DVCon Europe General Chair
I am pleased to welcome you all to the 3rd edition of DVCon India to be held September 15-16, 2016 at the Leela Palace Hotel, Bangalore.
DVCon India is a must-attend conference dedicated to design and verification of IPs, SoCs and electronic systems. The conference provides an excellent platform for attendees to discuss, network and contribute to the standards, flows and methodologies enabling silicon product realization. Following the grand success of DVCon U.S., the Indian edition of this conference has been receiving overwhelming response the last two years.
Today, the semiconductor industry is experiencing a major change in its landscape. In the post PC & mobile era, all eyes are on IoT which is an ecosystem of interconnected devices that are high on performance, low on power consumption, cheap and highly customized to end-user requirements. This requires a paradigm shift in how we design products enabling first silicon success faster than ever before. Starting from the concept exploration at the system level and bringing it down to the IPs interconnected on the SoC, DVCon India touches different aspects of design and verification. The discussions and information exchange cover a wide variety of topics, representing the latest developments and future trends in this domain.
The committee has worked relentlessly to come up with a 2-day packed agenda covering keynotes from industry luminaries, tutorials from the gurus, panel discussions with experts, papers and posters from the fraternity. Attendees are free to choose between ESL and DV tracks based on the topics of interest and learn further from what's next at the exhibitor stalls. Both of the days provide multiple opportunities to network and connect with peers in the industry. The technical sessions are spiced up with lot of fun at the gala dinner on day one. With a track record of more than 600 experts, representing 80+ organizations from all over the world, DVCon India is a unique conference for all members of the semiconductor ecosystem.
I am looking forward to meeting you and join hands to connect, contribute and celebrate at DVCon India 2016!
Gaurav Jalan, DVCon India General Chair
For more on DVCon India, read the "Breker Trekker" blog by Tom Anderson, DVCon India Promotions Co-Chair, in a recent issue of EDA Café.
Save the date! DVCon U.S. will be held February 27 to March 2, 2017 at the DoubleTree Hotel in San Jose, CA.
"DVCon U.S. continues to be the industry's leading forum for practicing design and verification engineers, managers and EDA tool suppliers to share advances in and application of design automation technology," stated Dennis Brophy, DVCon U.S. 2017 General Chair. "We look forward to a program full of engaging content in an atmosphere where presenters and attendees can share and discuss the very latest solutions to the most challenging issues impacting design productivity today."
All DVCon U.S. 2016 tutorials from Accellera Day are now available for download.
- The SVA Advanced Topics: SVAUnit and Assertions for Formal technical tutorial introduces advanced topics for assertion-based verification including SVAUnit and SVA for formal.
- The SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling tutorial provides an introduction to the concepts underlying the SystemVerilog-AMS language standard.
- Cut Your Design Time in Half with Higher Abstraction explains how to use SystemC to write synthesizable models at a higher level of abstraction than RTL.
- The UVM Tips and Tricks plus Preparing for IEEE UVM provide a plethora of tips and tricks to alleviate the struggle of debugging UVM test benches including both compile time and runtime tips.
With demand growing in the region, Accellera has added DVCon China in 2017. DVCon China will premier as a one-day event on April 19, 2017 at the Parkyard Hotel in Shanghai. With tremendous improvements in the IC industry in China in recent years, the timing is ideal to bring DVCon to Shanghai. The networking opportunities among peers and university students, as well as access to the vendors of advanced design and verification tools and services, is the hallmark of DVCon, and now China will benefit with the latest addition of DVCon. The conference has issued a Call for Abstracts with a deadline of November 1, 2016 and Call for Tutorials with a deadline of December 1, 2016.
"Welcome to China's Silicon Valley – Shanghai!" stated Andy Liu Hong Liang, DVCon China 2017 General Chair. "We will bring all that DVCon has to offer to our friends in China with an exciting in-depth technical program, and we'll give them the opportunity to learn and network among their peers. We recently issued the call for submissions and will have more announcements about our program coming soon. Let's enjoy and celebrate the first DVCon China together in the beautiful spring." Read the full welcome message >
(Translation: "Welcome to the grand event")
Martin Barnasconi has been a valuable member of Accellera working groups for more than 10 years. He has made significant contributions to several standards including SystemC, SystemC AMS, UVM-SystemC, multi-language and verification, and he is the current Chair of the SystemC AMS Working Group as well as an active member of the Accellera Board of Directors. As a champion for EDA and IP industry standards, Martin is a leader and visionary. Martin was a key force in launching a successful DVCon Europe in 2014, where he was also General Chair in 2014 and 2015. He was also the driving force behind the first SystemC Evolution Day in Munich this year.
Most recently, the release of the SystemC AMS standard as IEEE Std 1666.1-2016 in April is the result of many years of hard work and dedication by Martin and his team in the SystemC AMS Working Group. The SystemC AMS standard provides unique capabilities for the design and modeling of analog/mixed-signal applications at higher levels of design abstraction. As a result, SystemC AMS is a system-level mixed-signal modeling standard essential to the design of heterogeneous embedded systems where analog, digital and software functionality come together.
"Martin's influence and dedication within Accellera have been key to driving many standards forward as well as helping to grow the DVCon presence in Europe," stated Karen Pieper, Accellera Technical Committee Chair. "He and his group have committed more than a decade to actively developing the SystemC AMS standard, moving it forward and helping it to become wide-spread among the community. It is a testament to Martin's leadership that SystemC AMS has been released as IEEE 1666.1-2016. We are very proud of his dedication and oversight in getting it to this significant milestone."
As part of the Accellera-sponsored IEEE Get Program, IEEE 1666.1-2016 is available for download at no cost.
Approximately 184 engineers attended the annual SystemC Japan conference in June. The one-day conference was filled with 11 highly technical presentations followed by an evening reception that gave attendees an opportunity to talk directly with vendors.
All SystemC supplemental material, including material contributed under the SystemC Open Source License Agreement prior to the merger of the Open SystemC Initiative (OSCI) and Accellera in 2011, has now been relicensed under the Apache License, version 2.0. Many of the materials have been updated, the rest will follow soon. More information is available in our press release.
Stay tuned for a Portable Stimulus Tutorial Webinar coming in Q4! We will be sending out more details in the fall for this exciting three-part webinar series.
Presentations from the sold out SystemC Evolution Day conference, held May 3 in Munich, are now available for download.
2016 Global Sponsors
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Copyright 2016 Accellera Systems Initiative